The present invention relates to a quantizer design, and more particularly, to an analog-to-digital converter (ADC) with embedded noise-shaped truncation, embedded noise-shaped segmentation and/or embedded excess loop delay (ELD) compensation.
Analog techniques have dominated signal processing for years, but digital techniques are encroaching into this domain. An analog-to-digital converter (ADC) is needed to convert an analog signal into a digital signal, thus allowing the signal to be processed in a digital domain. The ADC may be used in a variety of applications. For example, a continuous-time delta-sigma modulator (CTDSM) has a quantizer implemented using an ADC. In general, a core part of the CTDSM is responsible for digitizing the analog input signal and reducing noise at lower frequencies. In this stage, the architecture implements a function called noise shaping that pushes low-frequency noise (e.g., quantization noise) up to higher frequencies outside the in-band (i.e., the band of interest).
To improve noise performance, reduce the power consumption and/or reduce the hardware complexity, several techniques have been proposed to add extra digital circuits to the CTDSM for applying additional digital processing to an ADC output (i.e., a quantizer output). However, the extra digital circuits introduce longer latency inevitably, thus resulting in a reduced excess loop delay (ELD) timing margin. As a result, these techniques are not applicable to a high-speed CTDSM with a stringent ELD timing margin requirement.